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Infineon and ST set milestone in wafer-level packaging industry standard
View£º4680 Release Date£º2022/9/1 16:17:39

¡¡¡¡Geneva,Switzerland,Singapore,and Neubiberg,Germany,August 11,2008--Infineon Technologies AG(FSE/NYSE:IFX),STMicroelectronics(NYSE:STM)and STATS ChipPAC(SGX-ST:STATSChP)announced today that three companies have signed an agreement to collaborate on the development of next-generation eWLB technology for the manufacture of future semiconductor products,building on Infineon¡¯s first-generation embedded wafer-level ball grid array(eWLB)technology.package.
¡¡¡¡Through Infineon's technology license agreement with STMicroelectronics and STATS ChipPAC,STMicroelectronics and Infineon,the world's two largest semiconductor leaders,have joined hands with STATS ChipPAC,a provider of advanced three-dimensional(3D)packaging solutions,to jointly develop the next-generation eWLB technology and fully develop The full potential of Infineon's existing eWLB packaging technology.The main R&D direction is to use both sides of a reconstituted wafer to provide semiconductor solutions with higher integration and higher number of contact units.
¡¡¡¡eWLB technology integrates the pre-process and post-process technologies of traditional semiconductor manufacturing,and processes all chips on the wafer synchronously in parallel processes,thereby reducing manufacturing costs.This technology will bring greater benefits in cost and size to the most advanced wireless products and consumer electronics.
¡¡¡¡The innovative eWLB technology can improve the integration of the package size and will become the industry standard for cost-effective and highly integrated wafer-level packaging.An important milestone in the development of an industry standard.ST plans to use this technology in several chips from the new joint venture ST-NXP Wireless and in other application markets,with sampling expected by the end of 2008 and early 2010 at the earliest Start mass production.
¡¡¡¡Carlo Cognetti,Director of Advanced Packaging Technology at STMicroelectronics,said:"eWLB technology complements our next-generation cutting-edge products,especially wireless chips.eWLB has established a number of advantages in technological innovation,cost competitiveness and size A new milestone.Together with Infineon,we will pave the way for eWLB to become the latest powerful packaging technology platform.¡±
¡¡¡¡Wah Teng Gan,Vice President of Infineon's Asia Pacific packaging and testing business,said:"We are delighted that ST has selected our state-of-the-art eWLB chip packaging technology,and we see this partnership as the greatest recognition of our excellence.As ST becomes Our new partners,coupled with the recognition of our innovative technology by STATS ChipPAC,a well-known 3D packaging technology leader,we predict that the packaging industry will be driven towards the development of energy-efficient and high-performance eWLB technology."
¡¡¡¡Han Byung Joon,Executive Vice President and Chief Technology Officer of STATS ChipPAC,said:"We are very pleased that Infineon and STMicroelectronics have chosen STATS ChipPAC as a partner to develop next-generation eWLB technology and to manufacture products using two generations of eWLB technology.The technical strengths of Feiling and STMicroelectronics,combined with our accumulated knowledge in advancing silicon wafer-level integration technology and flexibility,are necessary to bring this breakthrough technology to life."
¡¡¡¡About eWLB
¡¡¡¡eWLB is a revolutionary packaging technology launched by Infineon in the fall of 2007,which sets a new standard for the level of integration and energy efficiency in the chip packaging industry,paving the way for the semiconductor industry,to the industry and end consumers.Delivering a new generation of energy-efficient,high-performance mobile devices.With these new packaging processes,the benefits of Wafer Level Ball Grid Array(WLB)technology can be further expanded-namely optimized manufacturing costs and improved performance.As with WLB technology,all processing operations are done in parallel on the wafer,that is,all chips on the wafer are processed simultaneously through a single process.This advanced packaging technology is a new benchmark for integration and energy efficiency,and the size is smaller than traditional lead frame lamination The package shrinks by 30%,and the contact unit is increased by almost countless